New 'Lego-style' chip with stackable layers
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As we all know, in order to build a standard computer, in addition to the traditional central processing unit, memory, chipset, various I/O chips, etc. must be installed on the motherboard. On a circuit board that can realize standard computer functions, in addition to the above-mentioned various chips, a large amount of space needs to be set aside to complete the power supply, filtering and wiring work. Although this situation is harmless for application scenarios such as traditional desktop computers and data centers, for many emerging edge computing scenarios, the size limit is fatal.
With the continuous improvement of process and integration, the size of transistors is approaching the physical limit, and it is difficult to continue to rely on shrinking processes to improve performance and economic benefits. At the same time, the computing demand in artificial intelligence, Internet of Things, big data, 5G and other fields is increasing massively. How to break through the constraints of performance and volume has become a major challenge in the computing power era.
In the past, one of the solutions to this problem has been to cram more functionality into the same chip. However, in the process of practicing this method, with the increase of chip function and volume, the difficulty of chip design, testing and manufacturing is increasing exponentially. From this, the concept of 3D stacking of chips was proposed.
Recently, scientists at MIT have successfully designed a "Lego-style" chip. The chip's main innovation is that it uses optics rather than physical wires to transmit information. As a result, the chip can be reconfigured and component layers can be stacked, making it possible to add new processors, for example.
Lego blocks are a leisure hobby of many young people. Its unique charm lies in the fact that different objects can be built arbitrarily through the criss-cross of small squares. In the criss-crossing stack, we are limited only by our imagination. The chip adopts such an architecture, which can be reconfigured and stacked arbitrarily.
The chip has an area of 4 square millimeters, the size of a small scrap of paper, and there are 3 "blocks" for image recognition on the chip. Other types of chips, often connected by metal, allow alternating layers of sensing and processing elements to be connected to light-emitting diodes, replacing physical wire connections with optical communication systems, allowing for more flexibility in design, allowing chips to be stacked and added at will .
Therefore, the chip is not only small in size, but also greatly improved in performance. At present, the relevant research results have been published in the journal "Nature Electronics".